Intel oneAPI Quick Start Guide
This guide will walk you through the six steps required to use the Intel oneAPI FPGA toolkit on Noctua 2.
1. Get the examples.
The latest Intel oneAPI-samples are available on github. The master
branch of the repository is always under development for the next release and might be incompatible with the latest version installed on our systems. You can checkout a version specific branch that matches the oneAPI version you are going to use.
You can copy the files from our file system to speed-up the process with
cp -r /opt/software/FPGA/IntelFPGA/oneapi/24.1.0/oneAPI-samples .
cd oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile
or clone the repository and checkout the correct version with
git clone https://github.com/oneapi-src/oneAPI-samples.git
cd oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile
git checkout release/2024.1
2. Setup the local software environment on Noctua2.
module reset
module load fpga devel compiler
module load intel/oneapi/24.1.0
module load bittware/520n/20.4.0_hpc
module load CMake
module load GCC
3. Build and test the example in emulation.
Builds the emulation binary called fast_recompile.fpga_emu
.
Executes the emulation binary.
Note: the emulation in emulation gives no indication at all about the performance that is to be expected from hardware execution on a real FPGA.
4. Create and inspect reports as indicator of expected HW performance.
5. Build the hardware design (bitstream)
This hardware build step (so-called hardware synthesis) can take lots of time (hours!) and compute resources, so we create a batch script to submit the job to the slurm workload manager. Make sure to put your actual project acronym at the placeholder.
Then, we submit the synthesis_script.sh
to the slurm workload manager:
To speed-up the process and save resources for unnecessary synthesis we have pre-synthesized the design. Expand the box below to copy the pre-synthesized design for hardware execution.
6. Execute the hardware design on an FPGA.
After the hardware synthesis, we can allocate a suitably configured and equipped FPGA node and for execution.
To run the design, we load the proper modules and use the corresponding make command on the allocated FPGA node
How to proceed
For more information using the tools, refer to
Intel’s oneAPI Programming Guide and especially the FPGA flow,
and finally open-access book on Data Parallel C++.