When to consider FPGAs

Bit-level operations and data

FPGAs are always a promising architecture for applications where performance critical parts

use lots of bit-level operations (e.g. AND, OR, XOR, shifts)
or data can be encoded with few bits (e.g. DNA base pairs or amino acids, or binary/heavily quantized weights and inputs in neural networks).

A classical domain for FPGA acceleration is genome sequence alignment with the Smith-Waterman algorithm, where both the DNA base pairs and the scoring weights can be efficiently encoded in efficient custom bitwidth formats.
- One of the foundational publications about Smith-Waterman on FPGA from 2003 presents an approach with up to 814 GCUPS (Giga Cell Updates per Second) theoretical peak performance of the processing core on FPGA: https://link.springer.com/chapter/10.1007/978-3-540-45234-8_37
- In a recent adaptation on FPGA systems at PC2, up to 1663 GCUPs or up to 91.5 M complete alignment pairs were reported: https://ieeexplore.ieee.org/document/9556490
Cryptographic primitives for which no dedicated hardware accelerators exist can typically best be implemented on FPGAs and integrated into complete application flows. Examples: https://ieeexplore.ieee.org/abstract/document/6718394, https://ieeexplore.ieee.org/abstract/document/6861629, https://dl.acm.org/doi/abs/10.1145/3053687

Specific access patterns to on-chip memory

FPGAs can be a promising architecture for applications where CPUs or GPUs are not operating close to their peak performance due to inefficient usage of their cache hierarchy or shared memory.

PC2-Documentation

When to consider FPGAs

Bit-level operations and data

Specific access patterns to on-chip memory

Deterministic execution times for small chunks of work

Low-latency direct communication and overlap of execution and communication

Specific mix of arithmetic operations or mathematical functions