Software Overview
Overview
The software environment is setup using modules. Depending on the user requirements, different development flows for the FPGA cards are supported.
Xilinx Alveo U280
Vitis Design Flow (recommended)
Vivado Design Flow
Intel Stratix 10
oneAPI (recommended)
OpenCL (recommended for projects with exisiting OpenCL code base or for usage of serial channels)
DSP Builder
The development (including emulation to check functional correctness, report generation to get indications of expected performance, and synthesis with bittstream generation) can be done on any Noctua 2 node. Just load the corresponding modules for the target FPGA platform and Development Tool flow.
To execute designs on actual FPGAs, the same modules are required and additionally an FPGA node needs to be allocated with a fitting constraint, to get FPGAs with the expected configuration and drivers.
FPGA Software and Firmware Stacks (included page)
Constraint Overview (included page)
Usage: add constraint to any job allocation (srun, sbatch, salloc) in the FPGA partition where you plan to execute a design on the designated FPGA cards.
e.g. srun --partition=fpga --constraint=xilinx_u280_xrt2.12 -A [YOUR_PROJECT_ACCOUNT]
Xilinx Alveo U280 Nodes
Each node has 3 Xilinx Alveo U280 cards.
--constraint= |
|
|---|---|
| Configured with XRT 2.16 drivers and usable for designs built with Vitis 23.2 and Shell xdma_202211_1 |
| Further constraints named by xrt version. Refer to https://upb-pc2.atlassian.net/wiki/spaces/PC2DOK/pages/1903397 |
Intel Stratix 10 Nodes
Each node has 2 Bittware 520N cards.
--constraint= |
|
|---|---|
| Configured with BSP 20.4.0_max with external channels enabled. |
| Configured with BSP 20.4.0_hpc with external channels disabled. |
| Further constraints named by BSP version. Refer to https://upb-pc2.atlassian.net/wiki/spaces/PC2DOK/pages/1901981 and https://upb-pc2.atlassian.net/wiki/spaces/PC2DOK/pages/1903390 |
Emulation
Emulation works on all Noctua2 nodes. For the FPGA partition, it’s mandatory to specify a constraint. With the emulation constraint, you state that you don’t rely on any specific FPGA shell or device driver to be active.
--constraint= |
|
|---|---|
| Emulation only if you use the FPGA partition, but do not use the FPGA cards. |
FPGA and Tool Specific Details
Xilinx Alveo U280
Xilinx Vitis Design Flow
Xilinx Vivado Design Flow
You can use Vivado to create and simulate components via RTL that can be included as components into a Vitis project and the provided shells.
ml fpga
ml xilinx/vivadoIntel Stratix 10
Intel oneAPI Design Flow
Intel FPGA SDK for OpenCL Design Flow
Note: Intel FPGA SDK for OpenCL is no longer updated by Intel. Many of the command line tools from this SDK are still shipped with the current oneAPI tools and can be used to compile and execute OpenCL designs.
The Intel(R) FPGA SDK for OpenCL(TM) is setup using modules along with a Bittware (formerly Nallatech) BSP (including shell and drivers) with the respective commands:
module load intel/opencl_sdkmodule load bittware/520n
By default, the latest supported version is loaded. To use a specific version, you can append the version number like this:
module load intel/opencl_sdk/20.3.0
For any actual FPGA usage, the version of the BSP module (bittware_520n) version must match the node version allocated with a constraint.
Intel FPGA SDK for OpenCL and Bittware BSP version combinations
Identifying BSP versions of existing bitstreams
Intel OpenCL Quick Start Guide
The Intel FPGA SDK for OpenCL with further documentation by Intel. Relevant documentation includes in particular
DSP Builder for Intel FPGAs
You can use the Intel FPGA DSP builder to create and simulate components that can be included as components into an OpenCL or oneAPI project.
TODO: supported versions, modules, matlab
Intel Quartus Prime
You can use the Intel Quartus to create and simulate components that can be included as components into an OpenCL or oneAPI project.
TODO: supported versions, modules, licenses