Intel OpenCL Quick Start Guide
This guide will walk you walk you through the six steps required to use the Intel OpenCL FPGA toolkit on Noctua 2.
1. Get the latest examples.
We will use the vector_add
example code that is shipped with the Intel FPGA SDK for OpenCL.
We recommend working in /scratch/
because FPGA designs consume a considerable amount of disk space. Navigate to the directory assigned to your project under /scratch/
and create a working directory for this example:
cd /scratch/[DIRECTORY_ASSIGNED_TO_YOUR_PROJECT]
mkdir getting_started_with_fpgas
cd getting_started_with_fpgas
After, copy the vector_add
example into your getting_started_with_fpgas
workspace:
cp -r /opt/software/FPGA/IntelFPGA/opencl_sdk/21.4.0/hld/examples_aoc/common .
cp -r /opt/software/FPGA/IntelFPGA/opencl_sdk/21.4.0/hld/examples_aoc/vector_add .
2. Setup the local software environment on Noctua2.
3. Build and test the example in emulation.
The compilation is divided into two parts:
host code: executed on the CPU. Performs initialization, data handling and FPGA device setup. Host code is compiled with a regular GCC compiler.
kernel code: executed on the FPGA or often in emulation on the CPU.
In this step we will first compile the host code and then compile the kernel code for emulation on the CPU.
Builds the emulation binary called host
in the subdirectory bin
.
Now that the host code is generated, we can compile the kernel code:
Having the host and kernel compiled, we can execute the program:
Note: the emulation in emulation gives no indication at all about the performance that is to be expected from hardware execution on a real FPGA.
4. Create and inspect reports as indicator of expected HW performance.
To check if the kernel can be translated into an efficient FPGA design, intermediate files and an .html
report can be generated with the following command:
5. Build the hardware design (bitstream)
In this step we build the kernel code for an executed on the FPGA. This hardware build step (so-called hardware synthesis) can take lots of time (hours!) and compute resources, so we create a batch script to submit the job to the slurm workload manager.
Then, we submit the synthesis_script.sh
to the slurm workload manager:
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To speed-up the process and save resources for unnecessary synthesis we have pre-synthesized the design. Expand the box below to copy the pre-synthesized design for hardware execution.
6. Execute the hardware design on an FPGA.
After the hardware synthesis (and host code compilation), we can allocate a suitably configured and equipped FPGA node and for execution.
To run the design, we load the proper modules and use the corresponding command on the allocated FPGA node
Congratulations. You have executed a real program on an FPGA.
How to proceed
Now that you have successfully compiled and ran the example code on our FPGAs you can proceed in various directions
look into the source code of the
vector_add
example.try one of the other examples mentioned above. Start with an example that is as close as possible to the actual problem that you try to accelerate using FPGAs.
visit our main FPGA documentation page to learn more about the used parameters, other options and troubleshooting common problems.
do not hesitate to drop us an Email if you face any problems, need support or have any questions. Look for staff with Scientific Advisor FPGA Acceleration as their domain to contact the right person.