Overview

The software environment is setup using modules. Depending on the user requirements, different development flows for the FPGA cards are supported.

Xilinx Alveo U280
- Vitis Design Flow (recommended)
- Vivado Design Flow
Intel Stratix 10
- oneAPI (recommended)
- OpenCL (recommended for projects with exisiting OpenCL code base or for usage of serial channels)
- DSP Builder

The development (including emulation to check functional correctness, report generation to get indications of expected performance, and synthesis with bittstream generation) can be done on any Noctua 2 node. Just load the corresponding modules for the target FPGA platform and Development Tool flow.

To execute designs on actual FPGAs, the same modules are required and additionally an FPGA node needs to be allocated with a fitting constraint, to get FPGAs with the expected configuration and drivers.

FPGA Software and Firmware Stacks (included page)

This table provides an overview how the components for the different target platforms and development tools relate to each other.

Entries with ml <name> show modules that need to be loaded both for development and hardware execution with the respective FPGA platform and development tool. Here specific version names are omitted, which loads always the latest version of the module.

FPGA Platform		Xilinx Alveo U280 with Virtex Ultrascale+ FPGA	Bittware 520N with Intel Stratix 10 FPGA
Development Tool	This contains the compiler with high-level-synthesis features, report generation, and an emulator for testing. New optimizaiton features depend mostly on this tool.	Xilinx Vitits `ml xilinx/vitis`	Intel oneAPI `ml intel/oneapi`	Intel FPGA SDK for OpenCL `ml intel/opencl_sdk`
FPGA Synthesis Backend	This translates and maps your design to a bitstream, roughly the FPGA counterpart to an assembler in the CPU world. Since the FPGA backend has millions of registers, lookup tables and wires to chose from, this process takes a long time.	Xilinx Vivado, version selected and automatically loaded along with Vitis (above).	Intel Quartus, version selected and automatically loaded along with the BSP (below).
FPGA Shell	This component is configured on the FPGA and provides base funtionality like PCIe, and DDR or HBM2 controllers.	Xilinx shell `ml xilinx/u280`	Part of Bittware’s Board Support Package (BSP). `ml bittware/520n` Module combines FPGA shell and device driver. Available with external channels (suffix `_max`) and without (suffix `_hpc`) for direct FPGA-to-FPGA communication.
Device Driver	This is a software component that controls the interaction with the FPGA shell.	Xilinx XRT `ml xilinx/xrt`
Rules	This contains rules how suitable software and firmware stacks can be selected, if required.	A specific coupling of XRT and Vitis versions is recommended and automatically resolved by the modules (version strings don’t match). Multiple pairs of XRT+Vitis can use the same shell. Xilinx Vitis, XRT and U280 shell version combinations	Development tool needs a sufficiently recent, but not newer BSP version to work with. Intel oneAPI versions and Bittware BSP version combinations	Development tool needs a sufficiently recent, but not newer BSP version to work with. Intel FPGA SDK for OpenCL and Bittware BSP version combinations
Node Allocation Constraint	When you submit a job into the fpga partition for hardware execution, with this constraint you request a appropriately configured FPGA platform, shell and driver. You still need to load the corresponding modules. For synthesis and emulation, no constraint is needed, but you need to use the same modules as for later hardware execution.	Constraints named by FPGA card and driver (XRT) version `--constraint=xilinx_u280_xrt2.12`	Constraints named by FPGA card and shell/driver (BSP) version, with suffix for external channel configuration `--constraint=bittware_520n_20.4.0_max`
Quick Start Guides	These guides show how to get started with the platform and tool combination outlined in the corresponding column.	Xilinx Vitis Quick Start Guide	Intel oneAPI Quick Start Guide	Intel OpenCL Quick Start Guide
Vendor Tool Documentation	For the detailed documentation on using the development tools, we refer to the vendor documentation. Links to the respective overview pages and the actual technical guide(s) that are most fitting if you want to start an FPGA project.	Xilinx Vitis Overview Page Xilinx UG1393 Vitis Application Acceleration	Intel oneAPI Overview Page Intel oneAPI DPC++ FPGA Optimization Guide	Intel FPGA SDK for OpenCL Overview Page Intel FPGA SDK for OpenCL Programming Guide Intel FPGA SDK for OpenCL Best Practices Guide

Constraint Overview (included page)

Usage: add constraint to any job allocation (srun, sbatch, salloc) in the FPGA partition where you plan to execute a design on the designated FPGA cards.

e.g. srun --partition=fpga --constraint=xilinx_u280_xrt2.12 -A [YOUR_PROJECT_ACCOUNT]

Xilinx Alveo U280 Nodes
Intel Stratix 10 Nodes
Emulation

Xilinx Alveo U280 Nodes

Each node has 3 Xilinx Alveo U280 cards.

--constraint=
`xilinx_u280_xrt2.16`	Configured with XRT 2.16 drivers and usable for designs built with Vitis 23.2 and Shell xdma_202211_1
`xilinx_u280_xrt2.15` `xilinx_u280_xrt2.14` `xilinx_u280_xrt2.13` `xilinx_u280_xrt2.12` `xilinx_u280_xrt2.11` `xilinx_u280_xrt2.8`	Further constraints named by xrt version. Refer to Xilinx Vitis, XRT and U280 shell version combinations

Intel Stratix 10 Nodes

Each node has 2 Bittware 520N cards.

--constraint=
`bittware_520n_20.4.0_max`	Configured with BSP 20.4.0_max with external channels enabled.
`bittware_520n_20.4.0_hpc`	Configured with BSP 20.4.0_hpc with external channels disabled.
`bittware_520n_19.4.0_max` `bittware_520n_19.4.0_hpc` `bittware_520n_19.2.0_max` `bittware_520n_19.2.0_hpc` `bittware_520n_19.1.0_max` `bittware_520n_18.1.1_max` `bittware_520n_18.1.1_hpc`	Further constraints named by BSP version. Refer to Intel oneAPI versions and Bittware BSP version combinations and Intel FPGA SDK for OpenCL and Bittware BSP version combinations

Emulation

Emulation works on all Noctua2 nodes. For the FPGA partition, it’s mandatory to specify a constraint. With the emulation constraint, you state that you don’t rely on any specific FPGA shell or device driver to be active.

--constraint=
`emul`	Emulation only if you use the FPGA partition, but do not use the FPGA cards.

FPGA and Tool Specific Details

Xilinx Alveo U280

Xilinx Vitis Design Flow

Xilinx Vitis, XRT and U280 shell version combinations

Xilinx Vitis Quick Start Guide

Xilinx Vivado Design Flow

You can use Vivado to create and simulate components via RTL that can be included as components into a Vitis project and the provided shells.

ml fpga
ml xilinx/vivado

Intel Stratix 10

Intel oneAPI Design Flow

Intel oneAPI versions and Bittware BSP version combinations

Intel oneAPI Quick Start Guide

oneAPI GPU Plugins

Intel FPGA SDK for OpenCL Design Flow

The Intel(R) FPGA SDK for OpenCL(TM) is setup using modules along with a Bittware (formerly Nallatech) BSP (including shell and drivers) with the respective commands:

module load intel/opencl_sdk
module load bittware/520n

By default, the latest supported version is loaded. To use a specific version, you can append the version number like this:

module load intel/opencl_sdk/20.3.0

For any actual FPGA usage, the version of the BSP module (bittware_520n) version must match the node version allocated with a constraint.

Intel FPGA SDK for OpenCL and Bittware BSP version combinations

Identifying BSP versions of existing bitstreams

Intel OpenCL Quick Start Guide

The Intel FPGA SDK for OpenCL with further documentation by Intel. Relevant documentation includes in particular

Intel FPGA DSP Builder

You can use the Intel FPGA DSP builder to create and simulate components that can be included as components into an OpenCL or oneAPI project.

TODO: supported versions, modules, matlab

Intel Quartus Prime

You can use the Intel Quartus to create and simulate components that can be included as components into an OpenCL or oneAPI project.

TODO: supported versions, modules, licenses

Software Overview