...
The software environment is setup using modules. Depending on the user requirements, different development flows for the FPGA cards are supported.
...
FPGA Software and Firmware Stacks (included page)
| Include Page | |||
|---|---|---|---|
|
Constraint Overview (included page)
...
You can use Vivado to create and simulate components via RTL that can later be included as components into a Vitis project and the provided shells.
...
| Include Page | ||||
|---|---|---|---|---|
|
The Bittware (formerly Nallatech) BSP (including drivers) and the Intel(R) FPGA SDK for OpenCL(TM) are setup using modules with the respective commands:
| Code Block |
|---|
module load bittware_520n
module load intelFPGA_pro |
For any actual FPGA usage, the version of the BSP module (bittware_520n) version must match the node version allocated with the constraint. By default, the latest supported version is loaded. To use a specific version, you can append the version number like this:
| Code Block |
|---|
module load bittware_520n/19.4.0_hpc intelFPGA_pro/20.3.0 |
Matching SDK versions and BSP versions
The table below shows the full mapping of valid SDK to BSP versions for the Intel OpenCL design flow. Make sure to match the allocated constraint for real hardware execution.
...
bittware_520n modules
...
20.4.0_max/_hpc
...
19.4.0_max/_hpc
...
19.2.0_max/_hpc
...
19.1.0
...
18.1.1_max/_hpc
...
18.0.1
...
18.0.0
...
intelFPGA_pro modules
...
21.4.0
...
yes
...
21.3.0
...
yes
...
21.2.0
...
yes
...
21.1.0
...
yes
...
20.4.0
...
yes
...
yes
...
yes
...
yes
...
20.3.0
...
yes
...
yes
...
yes
...
20.2.0
...
yes
...
yes
...
yes
...
20.1.0
...
yes
...
yes
...
yes
...
19.4.0(_max/_hpc)
...
yes
...
yes
...
yes
...
yes
...
yes
...
yes
...
19.3.0
...
yes
...
yes
...
yes
...
yes
...
yes
...
19.2.0(_max/_hpc)
...
yes
...
yes
...
yes
...
yes
...
yes
...
19.1.0
...
yes
...
yes
...
yes
...
yes
...
18.1.1(_max/_hpc)
...
yes
...
yes
...
yes
...
18.0.1
...
yes
...
yes
...
18.0.0
...
yes
For the 19.2.0 and 18.1.1 tools, there are two versions of the BSP that target the same board. The *_max BSP enables the external serial channels and thus offers the default functionality for our setup. The *_hpc BSP does not offer external serial channels, but may enable higher clock frequencies for this tool version.
Identifying BSP versions of existing bitstreams
You can find out the constraint required for an existing bitstream using two commands of the aocl binedit tool, e.g.
| Code Block |
|---|
module load intelFPGA_pro
aocl binedit build/19_3/krn_auto/volume_dummy_v10.aocx print .acl.board
aocl binedit build/19_3/krn_auto/volume_dummy_v10.aocx print .acl.board_package |
Finding the output values of aocl binedit in the first two columns allows you to identify the constraint to be used.
...
.acl.board
...
.acl.board_package
...
--constraint
...
p520_max_sg280l
...
/cm/shared/opt/intelFPGA_pro/19.4.0/hld/board/bittware_pcie/s10
...
19.4.0_max
...
/cm/shared/opt/intelFPGA_pro/19.2.0/hld/board/bittware_pcie/s10
...
19.2.0_max
...
/cm/shared/opt/intelFPGA_pro/19.1/hld/board/bittware_pcie/s10
...
19.1.0
...
/opt/intelFPGA_pro/18.1.1/hld/board/nalla_pcie
...
18.1.1_max
...
/opt/intelFPGA_pro/18.0.1/hld/board/nalla_pcie
...
18.0.1
...
/opt/intelFPGA_pro/18.0.0/hld/board/nalla_pcie
...
18.0.0
...
p520_hpc_sg280l
...
/cm/shared/opt/intelFPGA_pro/19.4.0/hld/board/bittware_pcie/s10
...
19.4.0_hpc
...
/cm/shared/opt/intelFPGA_pro/19.4.0/hld/board/bittware_pcie/s10_hpc_default
...
19.4.0_hpc
...
/cm/shared/opt/intelFPGA_pro/19.2.0/hld/board/bittware_pcie/s10
...
19.2.0_hpc
...
/cm/shared/opt/intelFPGA_pro/19.2.0/hld/board/bittware_pcie/s10_hpc_default
...
19.2.0_hpc
...
/opt/intelFPGA_pro/18.1.1/hld/board/nalla_pcie
...
18.1.1_hpc
...
p520_max_sg280h
...
unsupported
...
p520_hpc_sg280h
...
unsupported
Unsupported BSPs: Since the 19.1.0 tools, the BSP comes with support for two different target boards: p520_max_sg280l and p520_max_sg280h. These differentiate between boards with so-called L-Tile and H-Tile FPGAs. Our boards contain L-Tile FPGAs, so only use p520_max_sg280l (and p520_hpc_sg280l for selected BSP versions) as targets for synthesis.
The Intel FPGA SDK for OpenCL with further documentation by Intel. Relevant documentation includes in particular
DSP Builder
supported versions
...
BSP
...
matlab
...
DSP Builder for Intel FPGAs
You can use the Intel FPGA DSP builder to create and simulate components that can be included as components into an OpenCL or oneAPI project.
TODO: supported versions, modules, matlab
Intel Quartus Prime
You can use the Intel Quartus to create and simulate components that can be included as components into an OpenCL or oneAPI project.
TODO: supported versions, modules, licenses