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Change Serial Channels during a running job

For the general usage of FPGA Serial Channels visit the main documentation page.

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First submit a job like normal. You can either start with the first topology or omit it and start without any intial links set:

Code Block
breakoutModewide
fpga-tester@n2login1:~
$ srun -A pc2-mitarbeiter --constraint=emulxilinx_u280_xrt2.15 -N 1 -p fpga -t 2:00:00 --pty zsh

or for the Bittware 520N partition also start with a specific initial topology:

Code Block
breakoutModewide
fpga-tester@n2login1:~
$ srun -A pc2-mitarbeiter --constraint=bittware_520n_20.4.0_max -N 1 -p fpga -t 2:00:00  --fpgalink=ringO --pty zsh

...

Code Block
breakoutModewide
fpga-tester@n2fpga17:~
$ module load fpga/changeFPGAlinks

Then you can run the commandchangeFPGAlinksXilinxfor the Alveo U280 partition or the commandchangeFPGAlinks. Again either for the Bittware 520N partition. The command names might be subject to changes / unification in the near future. You can run the command to specify a new topology, or run it without topology arguments to check the current status.

Examples for running the command without a topology (This will only generate a overview and not change anything, useful for documenting) or specify a topology (With the known --fpgalink= format) to set the links:

Code Block
breakoutModewide
fpga-tester@n2fpga03:~
$ changeFPGAlinksXilinx # Not changing anything, just checking
There are currently no links set up.
Your nodes in this Job (4743991):
	n2fpga03
No configuration change requested. Goodbye.

fpga-tester@n2fpga17:~
$ changeFPGAlinks # Not changing anything, just checking
Your current link-setup:
       n2fpga17:acl0:ch1-n2fpga17:acl1:ch0
       n2fpga17:acl0:ch3-n2fpga17:acl1:ch2
       n2fpga17:acl1:ch1-n2fpga17:acl0:ch0
       n2fpga17:acl1:ch3-n2fpga17:acl0:ch2

To visualize this configuration click here:
https://pc2.github.io/fpgalink-gui/index.html?import=n2fpga17%3Aacl0%3Ach1-n2fpga17%3Aacl1%3Ach0%20n2fpga17%3Aacl0%3Ach3-n2fpga17%3Aacl1%3Ach2%20n2fpga17%3Aacl1%3Ach1-n2fpga17%3Aacl0%3Ach0%20n2fpga17%3Aacl1%3Ach3-n2fpga17%3Aacl0%3Ach2%20

Your nodes in this Job (901745):
       n2fpga17
No configuration change requested. Goodbye.

Visualize here: Click!

Now Examples for running the command to specify a topology with the --fpgalink= syntax is used to change set the topologylinks:

Code Block
breakoutModewide
fpga-tester@n2fpga17:~
$ changeFPGAlinks --fpgalink=n00:acl0:ch0-n00:acl0:ch1 --fpgalink=n00:acl1:ch2-n00:acl1:ch3 --fpgalink=n00:acl1:ch0-n00:acl1:ch1 --fpgalink=n00:acl0:ch2-n00:acl0:ch3 # Change to custom topology
Your current link-setup:
       n2fpga17:acl0:ch1-n2fpga17:acl1:ch0
       n2fpga17:acl0:ch3-n2fpga17:acl1:ch2
       n2fpga17:acl1:ch1-n2fpga17:acl0:ch0
       n2fpga17:acl1:ch3-n2fpga17:acl0:ch2

To visualize this configuration click here:
https://pc2.github.io/fpgalink-gui/index.html?import=n2fpga17%3Aacl0%3Ach1-n2fpga17%3Aacl1%3Ach0%20n2fpga17%3Aacl0%3Ach3-n2fpga17%3Aacl1%3Ach2%20n2fpga17%3Aacl1%3Ach1-n2fpga17%3Aacl0%3Ach0%20n2fpga17%3Aacl1%3Ach3-n2fpga17%3Aacl0%3Ach2%20

Your nodes in this Job (901745):
       n2fpga17
Started changing link-config with ID 0defb6f3-244f-415d-8372-5eaa324b4aa0
START: Thu Sep 16 11:44:41 CEST 2021
INFO: Request from user "fpga-tester" from job "901745"
INFO: Nodelist of job: n2fpga17
INFO: Setting SPANK_FPGALINK0=n00:acl0:ch0-n00:acl0:ch1
INFO: Setting SPANK_FPGALINK1=n00:acl1:ch2-n00:acl1:ch3
INFO: Setting SPANK_FPGALINK2=n00:acl1:ch0-n00:acl1:ch1
INFO: Setting SPANK_FPGALINK3=n00:acl0:ch2-n00:acl0:ch3
Host list 
n2fpga17
Generated connections
fpgalink n2fpga17:acl0:ch0-n2fpga17:acl0:ch1
fpgalink n2fpga17:acl1:ch2-n2fpga17:acl1:ch3
fpgalink n2fpga17:acl1:ch0-n2fpga17:acl1:ch1
fpgalink n2fpga17:acl0:ch2-n2fpga17:acl0:ch3
Topology configuration request accepted after 0.205315113068s


To visualize this configuration click here:
https://pc2.github.io/fpgalink-gui/index.html?import=n2fpga17%3Aacl0%3Ach0-n2fpga17%3Aacl0%3Ach1%20n2fpga17%3Aacl1%3Ach2-n2fpga17%3Aacl1%3Ach3%20n2fpga17%3Aacl1%3Ach0-n2fpga17%3Aacl1%3Ach1%20n2fpga17%3Aacl0%3Ach2-n2fpga17%3Aacl0%3Ach3%20

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