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FPGA and Tool Specific Details

Xilinx Alveo U280

Xilinx Vitis Design Flow

Xilinx Vivado Design Flow

You can use Vivado to create and simulate components via RTL that can later be included into a Vitis project and the provided shells.

ml fpga
ml xilinx/vivado

Intel Stratix 10

Intel oneAPI Design Flow

Intel FPGA SDK for OpenCL Design Flow

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For any actual FPGA usage, the version of the BSP module (bittware_520n) version must match the node version allocated with the constraint. By default, the latest supported version is loaded. To use a specific version, you can append the version number like this:

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The table below shows the full mapping of valid SDK to BSP versions for the Intel OpenCL design flow. Make sure to match the allocated constraint for real hardware execution.

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