Intel FPGA SDK for OpenCL and Bittware BSP version combinations
Usage: select the desired combination of intelFPGA_pro and bittware_520n modules and load both individually
e.g. after loading the fpga gateway module with ml fpga
, invoke ml intel/intelFPGA_pro/21.4.0 bittware/520n
For hardware execution, an FPGA node must be allocated with a fitting constraint.
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| |||||||
---|---|---|---|---|---|---|---|---|
 | 20.4.0_max/_hpc | 19.4.0_max/_hpc | 19.2.0_max/_hpc | 19.1.0 | 18.1.1_max/_hpc | 18.0.1 | 18.0.0 | |
| 21.4.0 | yes, recommended | Â | Â | Â | Â | Â | Â |
21.3.0 | yes | Â | Â | Â | Â | Â | Â | |
21.2.0 | yes | Â | Â | Â | Â | Â | Â | |
21.1.0 | yes | Â | Â | Â | Â | Â | Â | |
20.4.0 | yes | yes | yes | yes | Â | Â | Â | |
20.3.0 | Â | yes | yes | yes | Â | Â | Â | |
20.2.0 | Â | yes | yes | yes | Â | Â | Â | |
20.1.0 | Â | yes | yes | yes | Â | Â | Â | |
19.4.0 | Â | yes | yes | yes | yes | yes | yes | |
19.3.0 | Â | Â | yes | yes | yes | yes | yes | |
19.2.0 | Â | Â | yes | yes | yes | yes | yes | |
19.1.0 | Â | Â | yes | yes | yes | yes | Â |
The *_max
BSP enables the external serial channels and thus offers the default functionality for our setup. The *_hpc
BSP does not offer external serial channels, but may enable higher clock frequencies for this tool version.