Xilinx Alveo U280
Relevant with current tools and shells
Software emulation of compute unit(s) exited unexpectedly
...
Note that after setting a specific limit within a job, you can not increase it again, only further decrease it.
Note that for most designs that eventually should run in hardware, 8 MB is either approaching or already exceeding the limits of available on-chip memory resources. However, there can be use cases where higher limits are useful, for example when emulating multiple kernels together that should eventually run on separate FPGAs.
Intel Stratix 10
CL_INVALID_PROGRAM_EXECUTABLE with fast emulation
When using the fast emulator along with host code that was previously tested with the legacy emulator and/or hardware execution, you may encounter a problem with during execution that corresponds to the OpenCL error code CL_INVALID_PROGRAM_EXECUTABLE. To fix this issue, your host code needs to invoke clBuildProgram (C API) or program.build() (C++ API). This invocation is required for any normal OpenCL code, but with legacy emulation and hardware execution, it was not required and could be skipped.
FPGA programmed with bitstreams built with different SDK versions in the same session
Error message during bitstream programming from host code or with aocl program
| Code Block |
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FAILED to read auto-discovery string at byte 2: Expected version is 19, found 20
Error: The currently programmed/flashed design is no longer supported in this release. Please recompile the design with the present version of the SDK and re-program/flash the board.
acl_hal_mmd.c:1460:assert failure: Failed to initialize kernel interfacemain: acl_hal_mmd.c:1460: l_try_device: Assertion `0' failed. |
This or similar error messages come up when invoking host code or aocl commands after a bitstream that was built with an earlier SDK version was configured. Workaround:
Load the latest intelFPGA_pro module (e.g. 19.3.0)
Configure the target bitstream (e.g. built with 19.2.0 SDK) using aocl program or your OpenCL host code
Optionally [reload the target intelFPGA_pro module that was used when building the bitstream]
Relevant with current tools and shells
ERROR: UNRECOGNIZED ERROR CODE (-1001)
This error might occur if the default system gcc (version 4.8) is used, see required gcc versions.
Data corrupted during transfer from FPGA global memory to the host
A bug can cause corruption of data that is transferred from FPGA global memory to the host. The issue only occurs seldomly, about once in 100-300 TiB of transferred data. An automatic detection and workaround is available. See Bittware 520N Data Transfer Issue and Workaround for more details.
Deadlock when emulating kernels using serial channels
Kernels that use the cl_intel_channels OpenCL extension and communicate via write_channel_intel and read_channel_intel might deadlock on emulation, depending on the order in which kernels attempt to read and write from a channel.
Workaround: load the module intel/channel_emulation_patch before running the emulation:
| Code Block |
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module load intel/channel_emulation_patch |
This module uses the LD_PRELOAD mechanism to hook into libc library calls and implement a workaround. Therefore all programs started while this module is loaded are potentially influenced. While we try to minimize the impact, we suggest to load this module solely when executing the emulation. If you notice any issues while the module is loaded, please get in contact with us.
LOCALE settings forwarded from your computer
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| Code Block |
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[tester@fe-1 matrix_mult]$ locale ... LC_NUMERIC="de_DE.UTF-8" // can cause above error [tester@fe-1 matrix_mult]$ export LC_NUMERIC="en_US.UTF-8" [tester@fe-1 matrix_mult]$ locale ... LC_NUMERIC="en_US.UTF-8" // known to work ... |
ERROR: UNRECOGNIZED ERROR CODE (-1001)
This error might occur if the default system gcc (version 4.8) is used, see required gcc versions.
Deadlock when emulating kernels using serial channels
Kernels that use the cl_intel_channels OpenCL extension and communicate via write_channel_intel and read_channel_intel might deadlock on emulation, depending on the order in which kernels attempt to read and write from a channel.
Workaround: load the module intel/channel_emulation_patch before running the emulation:
| Code Block |
|---|
module load intel/channel_emulation_patch |
This module uses the LD_PRELOAD mechanism to hook into libc library calls and implement a workaround. Therefore all programs started while this module is loaded are potentially influenced. While we try to minimize the impact, we suggest to load this module solely when executing the emulation. If you notice any issues while the module is loaded, please get in contact with us.
Data corrupted during transfer from FPGA global memory to the host
...
Relevant only with legacy tools or shells
CL_INVALID_PROGRAM_EXECUTABLE with fast emulation
When using the fast emulator along with host code that was previously tested with the legacy emulator and/or hardware execution, you may encounter a problem with during execution that corresponds to the OpenCL error code CL_INVALID_PROGRAM_EXECUTABLE. To fix this issue, your host code needs to invoke clBuildProgram (C API) or program.build() (C++ API). This invocation is required for any normal OpenCL code, but with legacy emulation and hardware execution, it was not required and could be skipped.
FPGA programmed with bitstreams built with different SDK versions in the same session
Error message during bitstream programming from host code or with aocl program
| Code Block |
|---|
FAILED to read auto-discovery string at byte 2: Expected version is 19, found 20
Error: The currently programmed/flashed design is no longer supported in this release. Please recompile the design with the present version of the SDK and re-program/flash the board.
acl_hal_mmd.c:1460:assert failure: Failed to initialize kernel interfacemain: acl_hal_mmd.c:1460: l_try_device: Assertion `0' failed. |
This or similar error messages come up when invoking host code or aocl commands after a bitstream that was built with an earlier SDK version was configured. Workaround:
Load the latest intelFPGA_pro module (e.g. 19.3.0)
Configure the target bitstream (e.g. built with 19.2.0 SDK) using aocl program or your OpenCL host code
Optionally [reload the target intelFPGA_pro module that was used when building the bitstream]