This guide will walk you walk you through the six steps required to use the Intel OpenCL FPGA toolkit on Noctua 2.
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Background: -rtl: Tells the compiler to stop after report generation.
-v: Shows more details during the generation
-board=p520_max_sg280l: Specifies the target FPGA board (Bittware 520N with Intel Stratix 10 GX 2800).
-board-package=/cm/shared/opt/intelFPGA_pro/20.4.0/hld/board/bittware_pcie/s10: Specifies the BSP in the correct version.
device/vector_add.cl: Kernel file for vector_add written in OpenCL.
-o vector_add_report: Output directory.
In order to inspect the report, you may want to copy the report to your local file system or mount your working directory, for more information refer to [Noctua2-FileSystems]. For example you can compress the report on Noctua 2: | Code Block |
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tar -caf vector_add_report.tar.gz vector_add_report/reports |
Then copy and decompress it from your local command line (e.g. Linux, MacOS, or Windows Subsystem for Linux): | Code Block |
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TBD
rsync -azv -e 'ssh -J <your-username>@fe.noctua.pc2.uni-paderborn.de' <your-username>@ln-0001:/scratch/<DIRECTORY_ASSIGNED_TO_YOUR_PROJECT>/getting_started_with_fpgas/vector_add/vector_add_report.tar.gz .
tar -xzf vector_add_report.tar.gz |
Open and inspect fpga_compile_report.prj/reports/report.html in your browser. The whole analysis contains little information, since the example is very simple. The main blocks of the report are Throughput Analysis -> Loop Analysis: displays information about all loops and their optimization status (is it pipelined? what is the initiation interval (II) of the loop?, …).
Area Analysis (of System): details about the area utilization with architectural details into the generated hardware.
Views -> System Viewer: gives an overall overview of your kernels, their connections between each other and to external resources like memory.
Views -> Kernel Memory Viewer: displays the data movement and synchronization in your code.
Views -> Schedule Viewer: shows the scheduling of the generated instructions with corresponding latencies.
Bottleneck Viewer: identifies bottlenecks that reduce the performance of the design (lower maximum clock frequency of the design (Fmax), increases the initiation interval (II), …).
Open and inspect vector_add_report/reports/report.html in your browser. The throughput analysis contains little information, since the example is very simple and ND-Range kernels as the one used in this example yield less details in the report than Single Work Item Kernels. The area analysis shows that the kernel system uses at most 1% of the available resources, much more complex or parallel kernels could fit on the FPGA. The system viewer shows two 32-bit Burst-coalesced load and one 32-bit Burst-coalesced store operations. Refer to Intel's documentation (in particular Programming and Best Practice guides) about the Intel FPGA for OpenCL to learn more about the properties and optimization goals in the report. |
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| title | Details and expected output with annotations |
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With --mem=32G, we allocate a small amount of main memory to this synthesis job, corresponding to the very small example we build here. For larger designs, typically at least 64G will be needed. You can check the progress of your job via squeue and after the job completes, check the complete job output in slurm-<jobid>.out.
Under the hood, the aoc command uses the following parameters -board=p520_max_sg280l: Specifies the target FPGA board (Bittware 520N with Intel Stratix 10 GX 2800).
-board-package=/cm/shared/opt/intelFPGA_pro/20.4.0/hld/board/bittware_pcie/s10: Specifies the BSP in the correct version.
device/vector_add.cl: Kernel file for vector_add written in OpenCL.
-o bin/vector_add.aocx: Synthesized output (configuration for the FPGA).
Expected output Note, that the build of the hardware design will create another report similar to the report that we discussed in the previous step. In contrast to the previous report, the new report contains the actual resource utilization of the design. |
To speed-up the process and save resources for unnecessary synthesis we have pre-synthesized the design. Expand the box below to copy the pre-synthesized design for hardware execution.
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| title | Copy pre-synthesized design |
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In order to still use the slurm workload manager, we use a modified batch script copy_pre-synthesed_design_script.sh and submit it. | Code Block |
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#!/bin/sh
# copy_pre-synthesed_design_script.sh
# Instead of starting the actual synthesis we use pre-synthezed results.
mv bin/vector_add_fpga.aocx bin/vector_add.aocx |
Then, we submit the copy_pre-synthesed_design_script.sh to the slurm workload manager: | Code Block |
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sbatch --partition=all -A <your_project_acronym> -t 00:10:00 ./copy_pre-synthesed_design_script.sh |
We submit into --partition=all. With -t 00:10:00, we allocate a small amount of time to this file copy job. You can check the progress of your job via squeue and after the job completes, check the complete job output in slurm-<jobid>.out.
Please notice that the compiled kernel has the same name for emulation and FPGA execution (that is vector_add.aocx). If you override the pre-synthesized design accidentally, you can submit the script again. |
6. Execute the hardware design on an FPGA.
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